1. Field of the Invention
The present invention generally relates to a method and device for generating test patterns used to test an integrated circuit such as an LSI (Large Scale Integrated) circuit. More particularly, the present invention is concerned with a method and device for efficiently generating a reduced number of test patterns making it possible to efficiently detect a defect in the LSI circuit without decrease in the reliability in defect detection.
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional test pattern generating device using an LSI simulator. The device shown in FIG. 1 is made up of a test pattern generating unit 1, an LSI simulator 2, a simulation result file 3 and a test pattern decision unit 4. The test pattern generating unit 1 generates test patterns. The LSI simulator 2 simulates an LSI circuit to be tested. The simulation result file 3 stores the results of the simulation, that is, the results of a decision on the output patterns obtained when the test patterns are applied to the LSI simulator 2. The test pattern decision unit 4 detects a defect in the LSI circuit on the basis of the output patterns output by the LSI simulator 2 by referring to the contents of the simulation result file 3.
FIG. 2 is a waveform diagram of test patterns generated by the test pattern generating unit 1. A reset signal RESET is generated by the test pattern generating unit 1, and resets sequential circuits such as flip-flops of LSI circuits of the LSI simulator 2 to initialize the flip-flops each time the reset signal RESET is switched to a low level. After the flip-flops are reset by the reset signal RESET, patterns A, B, . . . generated by the test pattern generating unit 1 are applied to terminals of the LSI circuits simulated by the LSI simulator 2. FIG. 2 also shows changes of the state of a flip-flop FF in response to the test patterns.
FIG. 3 is a diagram showing test patterns for use in detection of defects and defect detection object parts detected by the test patterns. In FIG. 3, FN1 through FN7 denote the names of the tests, and the numerals added to the character "P" in the parentheses denote the numbers of patterns of the related tests. A group of test patterns in each of the tests is supplied to the LSI simulalor 2 after the LSI simulator 2 is reset by the reset signal RESET shown in FIG. 2. In other words, a group of test patterns in each of the tests is supplied to the LSI simulator 2 while the reset signal is continuously at the high level after it is switched to the high level from the low level. Further, in FIG. 3, "a" through "m" denote the defect detection object parts. In other words, it is determined whether or not the defect detection object parts "a" through "m" are defective by using the tests FN1 through FN7.
FIG. 3 shows that defects in the defect detection object parts b, d and e can be detected by performing the test FN1 using 50 test patterns, and defects in the defect detection object parts d, f and i can be detected by performing the test FN2 using 50 test patterns. In the same manner as above, defects in the defect detection object parts a, b, d, e, f, g, h, i, j and k can be detected by the tests FN3 through FN7.
Turning now to FIG. 1 again, the test pattern generating unit 1 generates a group of test patterns A, B, . . . of one test after the flip-flops of the LSI circuit are reset by the reset signal RESET as shown in FIG. 2, and outputs these test patterns to the LSI simulator 2. The LSI simulator 2 receives the test patterns generated by the test pattern generator 1, and generates resultant output patterns, which are supplied to the test pattern decision unit 4. The test pattern decision unit 4 refers to the simulation result file 3 which stores the output patterns obtained when the test patterns of the tests are applied to the LSI simulator 2 beforehand, and outputs the defect detection results. For example, in the test named FN1 shown in FIG. 3, the test pattern decision unit 4 refers to the simulation result file 3, and confirms the detection of the defect detection parts b, d and e.
Normally, the tests FN1 through FN7 are designed to detect the respective object defects. When it is confirmed that a group of test patterns of a test can be used to detect the object defect, the test pattern generator 1 is designed to generate the group of test patterns. If a test having a group of test patterns more efficient than the tests FN1 through FN7 is created, the above test is added to the existing tests FN1 through FN7. In the above manner, new test patterns more efficient than the existing test patterns are added thereto.
In the above case, there is a possibility that some existing patterns may be meaningless due to the added efficient test patterns. There is also a possibility that a defective part is detected a plurality of number of times by different tests. Normally, all the tests are performed by using the respective test patterns, and hence it tales a long time to complete the test of the LSI circuit.